1. Field of the Invention
This invention relates to electronic circuits, and more particularly, clock divider circuits.
2. Description of the Related Art
Many computer systems use multiple clock signals having different periods. For example, it is not uncommon for the motherboard of a personal computer system to have a first clock signal of a first frequency, while a processor mounted on the motherboard operates at a second, higher clock frequency.
Production of the different clock signals may be accomplished in various ways. In some cases, separate crystal oscillators may be used to produce the different clock signals. In other cases, it may be desirable use a signal crystal oscillator, or other clock source, along with clock divider and/or multiplier circuitry. For example, if implementing a divide by four circuit, a typical approach may include the use of a first divide by two circuit as an input stage to generate a clock (clk) and a complementary signal, clock bar (!clk). The divide by two circuits may be implemented using D-type flip-flops. The clk and !clk signals from the input stage may then be forwarded to separate divide by two circuits. The outputs of the separate divide by two circuits may be phase shifted by 90xc2x0 from each other, which may be useful for producing additional clock signals.
With many circuits, it may be difficult to ensure an accurate 90xc2x0 phase shift between the signals (i.e. that one predetermined signals has a positive 90xc2x0 phase shift with respect to the other signal). For the circuits mentioned above, a reset or other control signal is normally used to initialize the circuit to a state which provides a predetermined phase shift of one signal from the other.
A clock divider circuit is provided. In one embodiment, the clock divider circuit may include a set of clocked circuits coupled to receive an input clock signal and a complement of the input clock signal. The clocked circuits may produce a first output clock signal and a second output clock signal that is phase shifted approximately a positive 90xc2x0 with respect to the first output clock signal. The clock divider circuit may be responsive only to the input clock signal. In other words, the clock divider circuit may not require a reset signal or other type of control signal in order to provide a predictable positive 90xc2x0 phase shift. The clock signals may also have approximately a 50% duty cycle. In one embodiment, the clock divider circuit may include a series coupled set of input circuits coupled to receive a clock signal and configured to generate the input clock signal and its complement.
In one embodiment, the clock divider circuit may include a pair of cross-coupled divide by two circuits. The divide by two circuits may include a plurality of clocked circuits which are configured to pass an input to an output on one phase of the clock cycle, and isolate the output from the input on another phase of the clock cycle. The clocked circuits may be passgates. The clocked circuits may be transparent during different phases of the clock cycle. For example, in one embodiment, a divide-by-4 circuit may include four passgates, two of which may be transparent during a clock phase opposite of that for which the other two passgates are transparent. This may result in a pair of output clock signals, wherein a designated one of the output clock signals has approximately a positive 90xc2x0 phase shift with respect to the other clock signal. The output clock signals may also have duty cycle which closely approximates 50% (e.g. about 0.1% error may be experienced in one implementation).